1. Field of the Invention
The present invention relates to the field of flat microtip display screens.
2. Discussion of the Related Art
FIG. 1 schematically shows the structure of a flat microtip screen of the type to which the present invention relates.
Such a microtip screen is essentially formed of a cathode 1 with microtips 2 and of a grid 3 provided with holes 4 corresponding to the locations of microtips 2. Cathode 1 is placed opposite to a cathodoluminescent anode 5, a glass substrate 6 of which generally forms the screen surface.
The cathode conductors are arranged in columns on a glass substrate 10. Microtips 2 are made on a resistive layer 11 deposited, for example, on the cathode conductors and are conventionally arranged within meshes defined by the cathode conductors. FIG. 1 partially shows the inside of a mesh, without showing the cathode conductors. Cathode 1 is associated with grid 3 which is organized in lines. The intersection of a line of grid 3 and of a column of cathode 1 defines a pixel.
This device uses the electric field created between cathode 1 and grid 3 to extract electrons from microtips 2 towards phosphor elements 7 of anode 5. In the case of a color screen such as shown in FIG. 1, anode 5 is provided with alternate strips of phosphor elements 7, each corresponding to a color (Red, Green, Blue). The strips are separated from one another by an insulator 8. Phosphor elements 7 are deposited on electrodes 9, formed of corresponding strips of a transparent conductive layer such as indium and tin oxide (ITO). The sets of red, green, blue strips are alternately biased with respect to cathode 1, so that the electrons extracted from the microtips 2 of a pixel of the cathode/grid are alternately directed to the phosphor elements 7 facing each of the colors. In the case of a monochrome screen (not shown), the anode is formed of a plane of phosphor elements of same color or of two sets of alternate strips of phosphor elements of same color.
The present invention more specifically relates to the cathode/grid of such a screen.
FIGS. 2A to 2D illustrate an example of conventional structure of a microtip screen cathode/grid, FIGS. 2B and 2D respectively being enlargements of portions of FIGS. 2A to 2C. Several microtips 2, for example, sixteen, are arranged in each mesh 12 defined by the cathode conductors 13 (FIG. 2B). The intersection of a line 14 of grid 3 and of a column 15 of cathode 1 here corresponds, for example, to sixty-four meshes 12 of a cathode pixel (FIG. 2A).
Cathode 1 is generally formed of layers successively deposited on glass substrate 10. FIGS. 2C and 2D partially show a cross-sectional view along line A-A' of FIG. 2B. A conductive layer is deposited on substrate 10. This layer is etched according to a column pattern 15, each column comprising meshes 12 surrounded with cathode conductors 13. A resistive layer 11 is then deposited on these cathode conductors 13. This resistive layer has the purpose of protecting each microtip 2 against an excess current upon starting of a microtip 2. Such a resistive layer 11 homogenizes the electron emission of the microtips 2 of a pixel of cathode 1 and thus increases its lifetime. The resistive layer is deposited, either on the conductive layer constitutive of the cathode conductors, or under this conductive layer, as described in document EP-A-0696045. An isolating layer 16 is deposited on resistive layer 11 to isolate cathode conductors 13 from grid 3 (FIG. 2D), formed in a conductive layer. Holes 4 and wells 17 are respectively made in layers 3 and 16 to receive microtips 2.
To avoid current leaks from one column of the cathode to another (which cause an excessive heating of the cathode likely to result in a screen breakage in operation), resistive layer 11 must, most often, be etched in columns corresponding to the columns (15, FIG. 2A) of the cathode. Such an etching requires a mask distinct from that used to make the cathode conductors, since the resistive layer is not meshed.
FIG. 3 schematically illustrates, in perspective view, an example of conventional addressing of a microtip screen.
For clarity, the meshing of columns K of cathode 1 has not been shown. Similarly, cathode 1 has been shown spaced apart from grid 3 whereas, in practice, the tops of microtips 2 reach holes 4 made in grid 3. Further, only nine microtips per pixel have been shown. In practice, they are several thousands per screen pixel. On the side of anode 5, the surfaces of pixels P have been shown in mixed lines.
The display of an image is performed during an image time (for example, 20 ms for a 50-hertz frequency) by properly biasing anode 5, cathode 1, and grid 3 by means of an electronic control circuit (partially shown for the grid control).
Concerning a monochrome screen anode 5, the plane of phosphor elements of the anode is permanently biased to a potential Va enabling to attract the electrons emitted by microtips 2. To choose this potential, the distance which separates the cathode/grid from the anode is especially taken into account, and this potential is, for example, on the order of 400 volts. For a color screen, the strips of phosphor elements of the anode are sequentially biased by sets of strips of a same color for a frame time corresponding to one third of the image time minus the times required for the switchings.
The display is performed line by line, by sequentially biasing the lines L of grid 3 for a "line time" during which each column K of cathode 1 is brought to a potential Vk which depends on the brightness of the pixel to be displayed along the current line (for example, Lj). The biasing of columns K of cathode 1 changes for each new line. A "line time" (for example, 40 .mu.s) corresponds to the duration of a frame divided by the number of lines L of grid 3. Current line Lj is brought to a potential +Vg (for example, 40 volts) for this line time whereas the other lines Lj-1, Lj+1 are at a potential .Vg (for example, -40 volts) during the line time. Columns K of the cathode are brought to respective potentials Vk(i-1), Vk(i), Vk(i+1) included between a maximum emission potential and a no emission potential (for example, respectively 0 and 0.40 volts) representing, for each line, the brightness of the pixel defined by the intersection of column K and of line L. The choice of the biasing potential values is linked to the characteristics of the phosphor elements and of the microtips. Conventionally, below a potential difference on the order of 40 volts between cathode 1 and grid 3, there is no electron emission, and the maximum emission used corresponds to a potential difference of approximately 80 volts.
The sequentially addressed lines of grid 3 are individually controlled by an amplifier 20, generally essentially formed of two P and N MOS transistors mounted in series between two supply lines at potentials +Vg and .Vg. The midpoint of the series association of the P and N transistors is connected to the grid line associated with amplifier 20 and the P-channel and N-channel MOS transistors, respectively, receive on their gates control signals (not shown) adapted to successively biasing the lines to high potential +Vg, all unaddressed lines being brought to low potential .Vg. It is indeed required to bring the unaddressed lines back to potential .Vg, to avoid that a previously addressed line be at a sufficient potential enabling to extract electrons.
A disadvantage of conventional screens is that the amplifiers 20 have to be made in CMOS technology, which increases the cost of the control circuit. Further, since one amplifier per line is required, the number of amplifiers made in CMOS technology is far from being negligible with respect to the bulk and to the global cost of the control circuit.
It has already been provided to simplify the structure of the control amplifiers of the grid lines by leaving the unaddressed lines at a floating potential. Such a solution requires the use, on the cathode side, of an additional column of microtips forming a so-called electrode of reset of the unaddressed grid lines. Such a solution is described in French patent application No. 2687841. In this patent application, the grid lines are prolonged on one side of the screen to an additional cathode column. This cathode column is addressed independently from the other columns and is brought, between each line time, to a sufficiently low potential with respect to the nominal grid biasing potential to enable an electron emission by this reset column. The electrons then emitted by the microtips of this column are meant to fall back on the grid line just addressed to lower its potential.
Although such a solution enables to use a single transistor per grid line addressing amplifier, it has several disadvantages.
First, this solution requires the addition of an additional cathode column, and this column must, in practice, be located outside the active screen area, that is, the display area, which increases the screen bulk. Further, the fact that the additional electrode is placed at one end of the grid line results in the potential lowering of the line just addressed being all the longest as the grid lines are long. Therefore, this document provides to add a second reset column at the other end of the screen. This further increases the bulk of the screen surface without being an optimal solution. Further, to provide reset columns distributed between the cathode display columns is an unadapted solution. First, the cathode display columns have to be spaced apart, which is prejudicial to the screen resolution, the reset column surfaces having to be large to emit a sufficient amount of electrons to quickly lower the grid line potential. Moreover, this complexifies the implementation of the anode, which must then be biased to a potential lower than the grid line addressing potential, to enable to repel the electrons emitted by the reset column towards the grid. Further, the electron emission by the additional column(s), between each line time, appears to be prejudicial to the screen lifetime.